a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having memory cells and logic circuits both formed on the same substrate, and its manufacture method.
b) Description of the Related Art
In a semiconductor device formed with both dynamic random access memories (DRAM) and logic circuits, a metal silicide film is formed on the source/drain regions and gate electrode of a MISFET in a the logic circuit area in order to improve the performance of logic circuits.
In order to improve the data storage characteristics of memory cells of a semiconductor device such as DRAM, it is desired to reduce junction leak current of source/drain regions. If a metal silicide film is formed on the source/drain regions, the junction leak current increases (refer to The 178-th Meeting, the Electro-chemical Society, pp. 218 to 220). Therefore, the metal silicide film is not formed generally during manufacture processes of DRAM.
In a semiconductor device formed with both DRAM and logic circuits, it is desired that a metal silicide film is not formed in the DRAM area but it is formed only in the logic circuit area.
In the DRAM area, the gate electrode of MISFET constituting a memory cell is generally formed integrally with a word line. In order to lower the resistance of the word line made of polysilicon or the like, it is desired to dope impurities at a high concentration. In the logic circuit area, however, a proper impurity concentration is determined from the threshold value or the like of MISFET. Therefore, the optimum impurity concentrations of the gate electrodes in the memory cell area and logic circuit area are not always coincident.
A precision of an electrostatic capacitance value of a capacitor in an analog circuit in the logic circuit area is desired to be made higher. From this reason, generally a three-layer structure of a polysilicon film/a silicon oxide film/a polysilicon fin is used. In order to reduce the voltage dependency of a capacitor, it is preferable to make the polysilicon film have a high impurity concentration. In order to suppress an increase in a manufacture cost, it is desired to suppress as much as possible an increase in the number of manufacture processes necessary for forming a polysilicon film of a high impurity concentration.
A method is known by which after only the memory cell area is formed, the logic circuit area is formed. If a bit line is disposed under the cell plate which is used as a common electrode of capacitors constituting memory cells, it is necessary that the front end of the bit line protrudes from the boarder of the cell plate in order to electrically connect the bit line and a wiring pattern in the logic circuit area. A process of removing an interlayer insulating film deposited in the logic circuit and a process of patterning a cell plate are therefore required to be executed separately when memory cells are formed.